PhD Thesis Defense: Yueh-Ching Teng

Friday, May 18, 2018, 10:00am

Rm. 102, Cummings Hall

“Design of CMOS front-end amplifier for electrical impedance applications”


Electrical Impedance Tomography (EIT) is a medical imaging methodology that does not need any kind of ionizing radiation and is significantly cheaper and smaller than Computerized Tomography (CT) or Magnetic Resonance Imaging (MRI). These advantages make EIT particularly suitable for emerging applications like continuous medical imaging and telemonitoring of organ function.

Current bench-top EIT systems are bulky and require shielded cables to interface with measurement electrodes. The cable introduces parasitic capacitance which shunts desired signals and degrades the accuracy of measurements. An EIT system based on application-specific integrated circuits (ASICs) can reduce the parasitic and stray capacitance within the measurement circuits, thus improving the system bandwidth and the measured signal quality.

This thesis presents the design of integrated circuit instrumentation amplifiers and techniques that are suitable for broadband ASIC-based EIT systems. Basic specifications and the amplifier design challenges are reviewed and addressed. The instrumentation amplifier must amplify the voltage difference between a pair of electrodes, while rejecting the large common mode interference that appears within the bandwidth of interest. Also, the instrumentation amplifier must process a wide dynamic range of input signals without sacrificing the temporal resolution (frame rate) of the imaging system. This thesis work involves the introduction of novel circuit designs and techniques, needed to achieve the desired amplifier performance. The proposed work also includes theoretical analyses of the novel approaches, as well as measurement results of prototype CMOS integrated circuit instrumentation amplifiers.

Thesis Committee

For more information, contact Daryl Laware at